This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
With today's high speed technology and ever-increasing demand on system performance, system downtime has a greater impact on business and technology than ever before. For systems having multiple central processing units (CPUs) coupled to each other and to various shared system components through a north bridge, a single CPU failure may negatively impact that entire system. In many cases, a CPU failure may result in a failure of the entire system. Even if the CPU failure does not cause a total system failure, the identification of the CPU failure, the repair of the CPU and/or the replacement of the CPU may require that the system be taken off line for a period of time. As previously described, this system downtime may negatively impact users. Further, in instances where CPUs are added or removed from a system, it is advantageous to provide features that are robust enough to allow for addition and removal of CPUs with minimal interruption of system functions. Minimizing system interruptions will enhance system performance and user satisfaction.